The present invention relates to nonvolatile semiconductor storage devices and, in particular, to a nonvolatile semiconductor storage device that can achieve improved accuracy of read operation and verify operation during rewrite.
In recent years, a large-capacity flash memory has been developed for the markets of memory cards and files. For the above uses, the flash memory is required to have high-speed read and high-speed rewrite functions at a high density and a reduced cost.
As a nonvolatile semiconductor storage device having the above-mentioned functions, there has been proposed a read/rewrite circuit construction of a NAND type flash memory by Symposium on VLSI Circuits Digest of Technical Papers pp. 20-21, 1992.
FIG. 11 shows the construction of the read/rewrite circuit of the above-mentioned NAND type flash memory.
This circuit has an open bit line structure with one centered read/write circuit 111, and verify circuits 112 and 113 are connected to each of the bit lines BLai and BLbi. The read/write circuit 111 operates as a flip-flop type sense amplifier in the read operation and the verify operation during rewrite and as a data latch circuit in the write operation. The control gate of a memory cell 204 is connected to an identical word line for every cell to be concurrently subjected to write.
Herein is mainly provided a description of the read operation and the verify operation during rewrite related to the present invention. In order to set the threshold voltage of the memory cell to a specified value in the write operation (or the erase operation), this verify operation during rewrite is to alternately execute the applying of a write pulse (or an erase pulse) and the verify operation. This verify operation during rewrite is basically the same as the read operation, while the threshold voltage value to be detected is changed.
The timing chart of FIG. 12 shows the timing of the read operation in the aforementioned NAND type flash memory. The timing chart of FIG. 12 shows an example in which the memory cell array (a) side is selected and the memory cell 204 is selected and subjected to read. A power voltage Vcc is assumed to be 3 V.
First of all, a voltage of ⅗ Vcc (1.8 V) is applied to a terminal Va, and a voltage of xc2xd Vcc (1.5 V) is applied to a terminal Vb.
Both control signals xcfx86pa and xcfx86pb to the gates of the transistors Tr1 and Tr2 have High level, and therefore, the transistors Tr1 and Tr2 are in the ON state. Accordingly, the potential of a selected bit line BLai is precharged with the voltage of ⅗ Vcc. On the other hand, the potential of a non-selected bit line BLbi, which is used as a dummy bit line for the open bit line system, is precharged with a voltage of xc2xd Vcc.
Then, the transistors Tr1 and Tr2 are put into the OFF state as shown in a period of t1 to t2 in FIG. 12. Subsequently, by making both control signals SG1 and SG2 to the gates of select transistors S1 and S2 have High level, both the transistors S1 and S2 are put into the ON state. Then, non-selected word lines CG1 through CG3 and CG5 through CG8 are set to the Vcc level, while a word line CG4 connected to the control gate of the selected memory cell 204 (to be subjected to read) is set to 0 V. In this stage, if the threshold voltage of the selected memory cell 204 is lower than 0 V (when the data of the memory cell 204 is xe2x80x9c0xe2x80x9d), then a current flows through the memory cell 204. Other memory cells having control gates (CG1 through CG3 and CG5 through CG8) to which the power voltage Vcc is applied are put into a state in which a cell current flows.
As described above, the current flows through the memory cell connected continuously to the memory cell 204, and therefore, the potential of the selected bit line BLai reduces to xc2xd Vcc level or less as indicated by the potential waveform xe2x80x9c0xe2x80x9d-read of the bit line BLai shown in FIG. 12 and continues to reduce.
Conversely, when the threshold voltage of the selected memory cell 204 is higher than 0 V (data of the memory cell 204 represents xe2x80x9c1xe2x80x9d), no cell current flows through the memory cell 204. Therefore, no current flows through the memory cell 204 even if the power voltage Vcc is applied to the control gates CG1, CG2, CG3 and CG5 through CG8 of other memory cells. Therefore, the potential of the selected bit line BLai does not reduce as indicated by the potential waveform xe2x80x9c1xe2x80x9d-read of BLai shown in FIG. 12, and ⅗ Vcc level is maintained. On the other hand, since no cell current flows as described above, the potential of the non-selected bit line BLbi, which is used as a dummy bit line here, maintains the xc2xd Vcc level.
When the threshold voltage of this memory cell 204 is lower than 0 V, the select transistors S1 and S2 are put in the OFF state and the non-selected word lines CG1 through CG3 and CG5 through CG8 are set to 0 V in accordance with a timing at which the potential of the selected bit line BLai sufficiently reduces and becomes 0 V as shown in a period of t2 to t3 (potential waveform xe2x80x9c0xe2x80x9d-read) in FIG. 12.
According to the description provided by way of example in FIGS. 11 and 12, the timing at which the potential reaches 0 V is merely of the operation of the memory cells 204 connected to the bit line BLai. However, even in the case of another memory cell or a memory cell connected to another bit line, the above-mentioned timing is the timing at which the selected bit line comes to have a voltage of 0 V when the data of the selected memory cell represents xe2x80x9c0xe2x80x9d.
Subsequently, both transistors TR3 and TR4 are put in the OFF state by control signals xcfx86p and xcfx86n to the gates of the transistors TR3 and TR4 provided on the power source side of the read/write circuit 111 in a period of t4 to t5 through the stable period of t3 through t4 in the circuit state shown in FIG. 12. By this operation, the read/write circuit 111 is reset and put into a floating state.
Subsequently, the control signal xcfx86e is made to have High level to turn on the transistors Tr5 and Tr6 and set (equalize) the potentials of a node a and a node b to a voltage of xc2xd Vcc. When this equalization is ended as in the period of t5 through t6 of FIG. 12, the control signal xcfx86e is set to 0 V to set back the transistors Tr5 and Tr6 to the OFF state.
When the transistors Tr7 and Tr8 are put in the ON state by making the clock signals xcfx86a and xcfx86b have High level, the bit line BLai is connected to the node a, and the bit line BLbi is connected to the node b.
By this operation, when the data of the memory cell 204 represents xe2x80x9c0xe2x80x9d, the bit line BLai of a potential of 0 V and the node a of the potential of xc2xd Vcc are connected to each other, and the potential of the node a starts to reduce from xc2xd Vcc to 0 V. When the data of the memory cell 204 represents xe2x80x9c1xe2x80x9d, the bit line BLai of the potential of ⅗ Vcc and the node a of the potential of xc2xd Vcc are connected to each other, and the potential of the node a starts to increase from xc2xd Vcc to ⅗ Vcc.
The non-selected bit line BLbi of the potential of xc2xd Vcc is also connected to the node b of the potential of xc2xd Vcc, and therefore, the potential of the node b maintains the potential of xc2xd Vcc (period of t6 to t7 of FIG. 12).
Subsequently, the transistor Tr4 provided on the ground voltage side of the read/write circuit 111 is turned on in a period subsequent to t7 of FIG. 12, and the transistor Tr3 provided on the power source Vrw side is subsequently turned on.
At this time, the potential of the node b is xc2xd Vcc. When the data of the memory cell 204 represents xe2x80x9c1xe2x80x9d, the potential of the node a is higher than the voltage of xc2xd Vcc. Conversely, when the data of the memory cell 204 represents xe2x80x9c0xe2x80x9d, the potential is lower than the voltage of xc2xd Vcc. Therefore, when the data of the memory cell 204 represents xe2x80x9c1xe2x80x9d, the flip-flop type read/write circuit 111 sets the node a at Vrw level and latches (senses) the node b at 0 V level.
Conversely, when the data of the memory cell 4 represents xe2x80x9c0xe2x80x9d, the read/write circuit 111 latches the node a at 0 V level and latches (senses) the node b at Vrw level.
When the transistors Tr9 and Tr10 are turned on by a signal from a column decoder 115, this sensed data is outputted from terminals 10A and 10B. This read is executed according to a page mode sequence.
According to the aforementioned prior art, it is required to establish the operation timing of the sense amplifier (read/write circuit 111) as shown in FIG. 12 by a control circuit or the like inside a chip in each of the read operation and the verify operation during rewrite as described above. Normally, this control circuit generates a timing signal of the sense operation in synchronization with a clock signal generated by an oscillator or the like inside the chip.
However, the frequency and so on of the circuit of the oscillator or the like have considerable variations due to the temperature and transistor characteristics, in accordance with which the timing signal also varies to reduce the read accuracy.
Moreover, since the threshold voltage of the cell varies depending on the temperature, and therefore, a threshold voltage distribution also varies. Therefore, it is required to provide a sufficient time margin in the sense operation in order to keep sufficient read accuracy.
Accordingly, the object of the present invention is to provide a nonvolatile semiconductor storage device capable of securing sufficient read accuracy without providing a sufficient sense time margin by logically generating the operation timing by a control circuit even when variations in temperature and transistor characteristics occur.
In order to achieve the aforementioned object, the present invention provides a nonvolatile semiconductor storage device including a plurality of word lines and a plurality of bit lines; a memory cell array where nonvolatile memory cells each having a control gate connected to one of the plurality of word lines and a drain connected to one of the plurality of bit lines are arranged in an array form; a sense amplifier section for amplifying data read on the bit line; a precharge circuit for precharging the bit line with a specified voltage; and a reference cell whose threshold value is preparatorily set to a specified value,
the nonvolatile semiconductor storage device executing data read or verify of rewrite data by precharging the bit line with the specified voltage by means of the precharge circuit, applying a specified read voltage or specified verify voltage to a selected word line and determining by means of the sense amplifier section whether or not the bit line is discharged by the selected nonvolatile memory cell, and
the nonvolatile semiconductor storage device comprising:
a bit line connected to the reference cell;
a sense circuit connected to the bit line of the reference cell for detecting a timing in which discharge of the bit line of the reference cell is completed; and
a timing control means for starting sensing the reference cell concurrently with starting sensing the selected nonvolatile memory cell, causing the sense circuit to detect a timing in which discharge of the bit line of the reference cell is completed and controlling sense operation termination timing of the sense amplifier section connected to the memory cell array on the basis of the detected timing of completion.
According to the present invention, when the characteristic of the nonvolatile memory cell shifts due to the influence of a temperature change or the like, the characteristic of the reference cell shifts so as to follow the shift of this characteristic. According to the present invention, the sense operation ending timing of the operation timing of the sense amplifier section in the read operation or verify operation is determined by the timing control means with the termination of the sense of the reference cell.
Therefore, according to the nonvolatile semiconductor storage device of the present invention, the relative read level of the nonvolatile memory cell does not change even if the characteristic of the nonvolatile memory cell shifts due to the influence of the temperature change or the like, and this obviates the need for providing a superfluous margin and allows high-accuracy read operation or verify operation to be achieved.
In one embodiment, the threshold value of the reference cell is the specified value between a lower limit of a threshold voltage distribution in a state in which each nonvolatile memory cell has a high threshold value and an upper limit of a threshold voltage distribution in a state in which each nonvolatile memory cell has a low threshold value, and
the data read is executed by applying the specified read voltage to the selected word line.
In one embodiment, the threshold value of the reference cell is a write verify voltage or an erase verify voltage of the nonvolatile memory cell, and
the verify of the rewrite data is executed by applying the verify voltage to the selected word line.
In one embodiment, the nonvolatile memory cells assume at least two states with respect to threshold voltage distribution thereof, and
the threshold voltage of the reference cell is set approximately at the middle of a lower limit of a threshold voltage distribution in a state in which the threshold voltages of the nonvolatile memory cells are high and an upper limit of a threshold voltage distribution in a state in which the threshold voltages of the nonvolatile memory cells are low.
According to this embodiment, when the threshold voltage of the nonvolatile memory cell shifts due to the temperature change or the like, the threshold voltage of the reference cell changes similarly to this change. Therefore, by setting the threshold voltage of the reference cell to a threshold voltage approximately at the middle of the upper limit of the one state and the lower limit of the other state of the memory cell array as in this embodiment, the relative read level of the memory cell can be made unchangeable. Therefore, according to this embodiment, there is no need for providing a superfluous margin for the sense timing during read, and this allows a high-accuracy read operation to be achieved.
Moreover, according to the present embodiment, the threshold voltage of the reference cell is set to a threshold voltage approximately intermediate between the upper limit and the lower limit of each state of the nonvolatile memory cells. For example, the threshold voltage of the reference cell takes a margin from the threshold voltage distribution in the state 0 and the threshold voltage distribution in the state 1. Therefore, even when the distribution of the threshold voltages of the nonvolatile memory cells is spread by disturb during rewrite, the threshold voltage of the reference cell does not overlap the threshold voltage of the nonvolatile memory cell, and a margin still exists. Therefore, the nonvolatile memory cell can surely be read, and reliability can be secured.
For example, in the case of a binary expression with the state 0 defined as a state in which the threshold voltages of the nonvolatile memory cells are high and the state 1 defined as a state in which the threshold voltages are low, the threshold voltage of the reference cell is set approximately at the middle of those states. Since the nonvolatile memory cell in this state 0 has a threshold voltage higher than that of the reference cell. Therefore, in the case where the discharge of the nonvolatile memory cell is terminated at the point of time when the discharge of the reference cell is ended in the read operation, the amount of current that can be flowed from this nonvolatile memory cell is smaller than the amount of current that can be flowed from the reference cell. Therefore, at the point of time when the discharge of the reference cell is terminated, the sense operation of the nonvolatile memory cell has not been terminated. However, since the memory cell in the state 1 has a threshold voltage lower than that of the reference cell, the amount of the current that can be flowed from the nonvolatile memory cell is larger than that of the reference cell. Therefore, in the memory cell in the state 1, the sense has been terminated at the point of time when the sense of the reference cell is ended.
In one embodiment, the nonvolatile memory cells assume at least two states with respect to threshold voltage distribution thereof, and the threshold voltage of the reference cell is set at upper limit of a threshold voltage distribution in a state in which the threshold voltages of the nonvolatile memory cells are low.
In this embodiment, for example, a nonvolatile memory cell has a binary expression with the state 0 defined as a state in which the threshold voltage of the nonvolatile memory cell is high and the state 1 defined as a state in which the threshold voltage is low, and the threshold voltage of the reference cell is set at the upper limit of the distribution of the threshold voltage of the state 1. It is to be noted that the operation to lower the threshold voltage of the nonvolatile memory cell from the state 0 to the state 1 is assumed to be the write operation.
In the case where the sense of the nonvolatile memory cell is terminated when the sense of the reference cell is ended in the write verify operation, the threshold voltage of the nonvolatile memory cell which has been put in the state 1 after the completion of write is lowered to a value lower than the threshold voltage of the reference cell. Therefore, this nonvolatile memory cell has a larger amount of current that can be flowed than in the reference cell, and the sense is terminated. However, the memory cell of which the write operation has not yet been terminated has a threshold voltage higher than that of the reference cell. Therefore, the current that can be flowed in the nonvolatile memory cell is smaller than in the reference cell, and the sense has not been terminated at the point of time when the sense of the reference cell is ended. Therefore, the write is executed again.
By thus setting the threshold voltage of the reference cell to the threshold voltage at the upper limit of the threshold voltage distribution of the state in which the threshold voltages of the nonvolatile memory cells are low, there is no need for providing a superfluous margin for the operation timing of the sense amplifier in the verify operation, and this allows the accuracy of the verify operation to be improved.
In one embodiment, the nonvolatile memory cells assume at least two states with respect to threshold voltage distribution thereof, and the threshold voltage of the reference cell is set at a lower limit of a threshold voltage distribution in a state in which the threshold voltages of the nonvolatile memory cells are high.
According to this embodiment, for example, a nonvolatile memory cell has a binary expression with the state 0 defined as a state in which the threshold voltage thereof is high and the state 1 defined as a state in which the threshold voltage is low, and the threshold voltage of the reference cell is set at the lower limit of the threshold voltage distribution of the state 0. It is to be noted that the operation for raising the threshold voltage of the nonvolatile memory cell from the state 1 to the state 0 is assumed to be the erase operation.
At this time, the nonvolatile memory cell put in the state 0 with the erase completed has been raised to the point of a threshold voltage higher than that of the reference cell. Therefore, in the case where the sense of the nonvolatile memory cell is terminated at the time when the sense of the reference cell is ended in the erase verify operation, it is determined that the nonvolatile memory cell is in the state 0 since the amount of current that can be flowed in the nonvolatile memory cell is less than in the reference cell and the electric charges precharged in the bit line are not sufficiently pulled. On the other hand, the nonvolatile memory cell in which the erase operation has not yet been terminated has a threshold voltage lower than that of the reference cell. Therefore, the amount of current that can be flowed in the nonvolatile memory cell is greater than in the reference cell, and the electric charges precharged in the bit line are sufficiently pulled. Therefore, it is determined that this memory cell is in the state 1, and erase is executed again.
As described above, by setting the threshold voltage of the reference cell at the lower limit of the threshold voltage distribution of the state 0 of the nonvolatile memory cells, there is no need for providing a superfluous margin for the timing of the sense operation in the verify operation, and this allows the accuracy of the verify operation to be improved.
In one embodiment, the reference cell is formed in a region that is electrically separated from the nonvolatile memory cells.
According to this embodiment, the reference cell is formed in the region that is electrically separated from the nonvolatile memory cells, and therefore, the reference cell receives no needless disturb. Therefore, the threshold voltage of the reference cell does not fluctuate, and the reliability is improved.
In one embodiment, a sense circuit is provided in correspondence with each of the bit lines of the nonvolatile memory cells and constructed so as to collectively read or verify the plurality of nonvolatile memory cells of which control gates are commonly connected to the same word line, and
the reference cell is provided in correspondence with each of the word lines.
According to this embodiment, the read operation of the nonvolatile memory cell and the reference cell are executed by the same word line, and therefore, the memory cell and the reference cell are sensed by quite the same word line voltage. Therefore, the read accuracy can be improved.
In one embodiment, the reference cell is arranged farther apart from a decoder for controlling the word line than the nonvolatile memory cells.
According to this embodiment, the read operation that covers the margin due to the shift in rise time of the word line can be executed, and the read accuracy is improved.
A nonvolatile semiconductor storage device of one embodiment comprises a delay means for delaying a signal detected by the sense circuit connected to the reference cell before using the detected signal as a sense terminate signal of the nonvolatile memory cells that constitute the memory cell array.
According to this embodiment, the aforementioned delay time can be set to a time in which the variations in the characteristics of the reference cell and the nonvolatile memory cells in the memory cell array or the variations between the nonvolatile memory cells inside the memory cell array are absorbed. With this delay time setting, the read accuracy can be improved by absorbing the above-mentioned characteristic variations and removing the superfluous margin of the sense operation. Moreover, by optimizing the delay time, the improvement in read accuracy and the removal of the superfluous (excessive) read margin can be achieved, and the speed of read can be increased.